| #1195597 in Books | 2013-04-14 | 2013-10-04 | Original language:English | PDF # 1 | 9.25 x.86 x6.10l,1.17 | File type: PDF | 354 pages||7 of 7 people found the following review helpful.| Some interesting parts, but mostly a collection of 'tricks'.|By Customer|This book covers many facets of the task of creating testbenches. However, it doesn't seem to follow a very well thought out plan, and there are holes in the coverage.
Most of the book is a 'tips and tricks' coverage of how to get each language to do what it wasn't designed to do. He walks th||"The bible for techniques in writing effective, readable and reusable Verilog and VHDL testbenches within a best-in-class verification process." Ben Cohen - VHDLCohen Training
CHAPTER 6 Architecting Testbenches 221 Reusable Verification Components 221 Procedural Interface 225 Development Process 226 Verilog Implementation 227 Packaging Bus-Functional Models 228 Utility Packages 231 VHDL Implementation 237 Packaging Bus-Functional Procedures 238 240 Creating a Test Harness 243 Abstracting the Client/Server Protocol Managing Control Signals 246 Multiple Server Instances 247 Utility Packages 249 Autonomous Generation and Monitoring 250 Autonomous...
You easily download any file type for your gadget.Writing Testbenches: Functional Verification of HDL Models | Janick Bergeron. I have read it a couple of times and even shared with my family members. Really good. Couldnt put it down.
